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cy62177dv30 mobl ? 32-mbit (2 m 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number : 38-05633 rev. *g revised july 20, 2012 features very high speed: 55 ns wide voltage range: 2.20 v?3.60 v ultra-low active power ? typical active current: 2 ma at f = 1 mhz ? typical active current: 15 ma at f = f max ultra low standby power easy memory expansion with ce 1 , ce 2 and oe features automatic power-down when deselected complementary metal oxide semiconductor (cmos) for optimum speed/power packages offered in a 48-ball fine ball grid array (fbga) functional description the cy62177dv30 is a high-performance cmos static ram organized as 2m words by 16 bits. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones.the device also has an automatic power-down feature that significantly reduces power consumption. the device can also be put into standby mode when deselected (ce 1 high or ce 2 low or both bhe and ble are high). the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected (ce 1 high or ce 2 low), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or during a write operation (ce 1 low, ce 2 high and we low). writing to the device is accomp lished by taking chip enables (ce 1 low and ce 2 high) and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 20 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 20 ). reading from the device is accomplished by taking chip enables (ce 1 low and ce 2 high) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table for a complete description of read and write modes. logic block diagram 2048k 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data-in drivers oe a 4 a 3 i/o 8 ?i/o 15 we ble bhe a 16 a 0 a 1 a 17 a 9 a 18 a 10 power-down circuit ce 2 ce 1 a 20 a 19
cy62177dv30 mobl ? document number : 38-05633 rev. *g page 2 of 13 contents pin configuration .............................................................. 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics over the operating range ... 4 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics (over the operating range) ............................................. 5 data retention waveform ................................................. 6 switching characteristics over the operating range .. 6 switching waveforms ...................................................... 7 truth table ..................................................................... 10 ordering information ...................................................... 10 ordering code definitions ..... .................................... 10 package diagram ............................................................ 11 reference information ................................................... 11 acronyms .................................................................. 11 document conventions ......... .................................... 11 document history page ................................................. 12 sales, solutions, and legal information ...................... 13 worldwide sales and design s upport ......... .............. 13 products .................................................................... 13 psoc solutions ......................................................... 13
cy62177dv30 mobl ? document number : 38-05633 rev. *g page 3 of 13 pin configuration [1] figure 1. 48-ball fbga top view product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( ? a) f = 1 mhz f = f max min typ [2] max typ [2] max typ [2] max typ [2] max cy62177dv30ll 2.2 3.0 3.6 55 2 4 15 30 5 50 notes 1. dnu pins have to be left floating or tied to vss to ensure proper application. 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25 c. we a 11 a 10 a 6 a 0 a 3 ce 1 i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe vss a 7 i/o 0 bhe ce 2 a 17 a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 19 a 18 a 20 3 2 6 5 4 1 d e b a c f g h a 16 dnu vcc
cy62177dv30 mobl ? document number : 38-05633 rev. *g page 4 of 13 maximum ratings exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. storage temperature ............................... ?65 c to + 150 c ambient temperature with power applied .......................................... ?55 c to + 125 c supply voltage to ground potential ...... ?0.3 v to v cc + 0.3 v dc voltage applied to outputs in high z state [3, 4] ............................... ?0.3 v to v cc + 0.3 v dc input voltage [3, 4] ............................ ?0.3 v to v cc + 0.3 v output current into outputs (low) .............................. 20 ma static discharge voltage........................................... >2001 v (per mil-std-883, method 3015) latch-up current..................................................... . >200 ma operating range device range ambient temperature v cc [5] cy62177dv30ll industrial ?40 c to +85 c 2.20 v to 3.60 v electrical characteristics over the operating range parameter description test conditions min typ [6] max unit v oh output high voltage i oh = ?0.1 ma v cc = 2.20 v 2.0 ? ? v i oh = ?1.0 ma v cc = 2.70 v 2.4 ? ? v v ol output low voltage i ol = 0.1 ma v cc = 2.20 v ? ? 0.4 v i ol = 2.1 ma v cc = 2.70 v ? ? 0.4 v v ih input high voltage v cc = 2.2 v to 2.7 v 1.8 ? v cc +0.3 v v v cc = 2.7 v to 3.6 v 2.2 ? v cc +0.3 v v v il input low voltage v cc = 2.2 v to 2.7 v ?0.3 ? 0.6 v v cc = 2.7 v to 3.6 v ?0.3 ? 0.8 v i ix input leakage current gnd ? v i ? v cc ?1 ? +1 ? a i oz output leakage current gnd ? v o ? v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma cmos levels 15 30 ma f = 1 mhz 2 4 ma i sb1 automatic ce power-down current?cmos inputs ce 1 ? v cc ? 0.2 v, ce 2 < 0.2 v, v in ? v cc ?0.2 v, v in ? 0.2 v) f = f max (address and data only), f = 0 (oe , we , bhe and ble ), v cc = 3.60 v ?5100 ? a i sb2 automatic ce power-down current?cmos inputs ce 1 ? v cc ?? 0.2 v, ce 2 < 0.2 v, v in ?? v cc ? 0.2 v or v in ?? 0.2 v, f = 0, v cc = 3.60 v ?550 ? a notes 3. v il(min.) = ?2.0 v for pulse durations less than 20 ns. 4. v ih(max) = v cc + 0.75 v for pulse durations less than 20 ns. 5. full device ac operation requires linear v cc ramp from 0 to v cc(min) ? 500 ? s. 6. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25 c
cy62177dv30 mobl ? document number : 38-05633 rev. *g page 5 of 13 capacitance parameter [7] description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 12 pf c out output capacitance 12 pf thermal resistance parameter [7] description test conditions bga unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 55 ? c/w ? jc thermal resistance (junction to case) 16 ? c/w ac test loads and waveforms v cc v cc output r2 50 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: th venin equivalent all input pulses r th r1 parameters 2.5 v (2.2 v to 2.7 v) 3.0 v (2.7 v to 3.6 v) unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v data retention characteristics (over the operating range) parameter description conditions min typ [8] max unit v dr v cc for data retention 1.5 ? ? v i ccdr data retention current v cc = 1.5 v ce 1 ? v cc ?? 0.2 v, ce 2 < 0.2 v, v in ? v cc ? 0.2 v or v in ? 0.2 v ??25 ? a t cdr [7] chip deselect to data retention time 0? ?ns t r [9] operation recovery time 55 ? ? ns notes 7. tested initially and after any design or process changes that may affect these parameters. 8. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25 c 9. full device operation requires linear v cc ramp from v dr to v cc(min.) ? 100 ? s or stable at v cc(min.) ? 100 ? s.
cy62177dv30 mobl ? document number : 38-05633 rev. *g page 6 of 13 data retention waveform [10, 11] v cc , min. v cc , min. t cdr v dr ? 1.5 v t r ce or v cc bhe . ble data retention mode switching characteristics over the operating range parameter [11, 12] description min max unit read cycle t rc read cycle time 55 ? ns t aa address to data valid ? 55 ns t oha data hold from address change 10 ? ns t ace ce low to data valid ? 55 ns t doe oe low to data valid ? 25 ns t lzoe oe low to low z [13] 5 ? ns t hzoe oe high to high z [13, 14] ? 20 ns t lzce ce low to low z [13] 10 ? ns t hzce ce high to high z [13, 14] ? 20 ns t pu ce low to power-up 0 ? ns t pd ce high to power-down ? 55 ns t dbe ble /bhe low to data valid ? 55 ns t lzbe ble /bhe low to low z [13] 10 ? ns t hzbe ble /bhe high to high z [13, 14] ? 20 ns write cycle [15] t wc write cycle time 55 ? ns t sce ce low to write end 40 ? ns t aw address set-up to write end 40 ? ns t ha address hold from write end 0 ? ns t sa address set-up to write start 0 ? ns t pwe we pulse width 40 ? ns t bw ble /bhe low to write end 40 ? ns t sd data set-up to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [13, 14] ? 20 ns t lzwe we high to low z [13] 10 ? ns notes 10. bhe .ble is the and of both bhe and ble . chip can be deselected by either disabling the chip enable signals or by disabling both bhe and ble . 11. ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 12. test conditions for all parameters other than tri-state parame ters assume signal transition time of 1 ns/v, timing reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ.) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? section. 13. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 14. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedance state. 15. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the dat a input set-up and hold timing should be referenced to the edge o f the signal that terminates the write.
cy62177dv30 mobl ? document number : 38-05633 rev. *g page 7 of 13 switching waveforms [16] figure 2. read cycle 1 (address transition controlled) [17, 18] figure 3. read cycle 2 (oe controlled) [18, 19, 20] notes 16. all read/write switching waveforms are shown for 16-bit data transactions only. 17. the device is continuously selected. oe , ce = v il , bhe and/or ble = v il . 18. we is high for read cycle. 19. address valid prior to or coincident with ce , bhe , ble transition low. 20. ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. address data i/o previous data valid valid data out t rc t aa t oha 50% 50% valid data out t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd high oe ce i cc i sb impedance address v cc supply current t hzbe bhe / ble t lzbe t hzce data i/o t dbe
cy62177dv30 mobl ? document number : 38-05633 rev. *g page 8 of 13 figure 4. write cycle 1 (we controlled) [21, 22, 23, 24, 25] figure 5. write cycle 2 (ce controlled) [21, 22, 23, 24, 25] notes 21. data i/o is high impedance if oe = v ih . 22. if ce goes high simultaneously with we = v ih , the output remains in a high-impedance state. 23. during this period, the i/os are in output state and input signals should not be applied. 24. ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 25. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data i nput set-up and hold timing should be referenced to the edge o f the signal that terminates the write. switching waveforms [16] (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data in ce address we data i/o oe bhe / ble t bw see note 23 t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data in ce address we data i/o oe see note 23 bhe /ble t bw t sa
cy62177dv30 mobl ? document number : 38-05633 rev. *g page 9 of 13 figure 6. write cycle 3 (we controlled, oe low) [26, 27, 28] figure 7. write cycle 4 (bhe /ble controlled, oe low) [26, 27, 28] notes 26. ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 27. if ce goes high simultaneously with we = v ih , the output remains in a high-impedance state. 28. during this period, the i/os are in output state and input signals should not be applied. switching waveforms [16] (continued) valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o t bw bhe / ble see note 28 data i/o address t hd t sd t sa t ha t aw t wc ce we valid data t bw bhe /ble t sce t pwe see note 28
cy62177dv30 mobl ? document number : 38-05633 rev. *g page 10 of 13 truth table ce 1 ce 2 we oe bhe ble inputs/outputs mode power h x x x x x high z deselect/power-down standby (i sb ) x l x x x x high z deselect/power-down standby (i sb ) x x x x h h high z deselect/power-down standby (i sb ) l h h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) l h h l h l data out (i/o 0 ?i/o 7 ); high z (i/o 8 ?i/o 15 ) read active (i cc ) l h h l l h high z (i/o 0 ?i/o 7 ); data out (i/o 8 ?i/o 15 ) read active (i cc ) l h h h l h high z output disabled active (i cc ) l h h h h l high z output disabled active (i cc ) l h h h l l high z output disabled active (i cc ) l h l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l h l x h l data in (i/o 0 ?i/o 7 ); high z (i/o 8 ?i/o 15 ) write active (i cc ) l h l x l h high z (i/o 0 ?i/o 7 ); data in (i/o 8 ?i/o 15 ) write active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 55 CY62177DV30LL-55BAXI 51-85191 48-ball fbga (8 mm 9.5 mm 1.2 mm) (pb-free) industrial ordering code definitions cy 621 7 7d ll 55 bax i company id: cy = cypress mobl sram family density = 32 mbit bus width = x16 d = 130nm technology speed grade = 55ns package type = bax :48-ball fbga (pb-free) temperature grade i = industrial low power v30 voltage range (3 v typical)
cy62177dv30 mobl ? document number : 38-05633 rev. *g page 11 of 13 reference information acronyms document conventions units of measure package diagram figure 8. 48 ball fbga (8 9.5 1.2 mm) (51-85191) 51-85191 *b acronym description cmos complementary metal oxide semiconductor i/o input/output sram static random access memory fbga fine ball grid array symbol unit of measure c degrees celsius ? a microampere ma milliampere mhz megahertz ns nanosecond pf picofarad v volt ? ohm w watt
cy62177dv30 mobl ? document number : 38-05633 rev. *g page 12 of 13 document history page document title: cy62177dv30 mobl ? 32-mbit (2 m 16) static ram document #: 38-05633 revision ecn orig. of change submission date description of change ** 251075 aju see ecn new datasheet *a 330363 aju see ecn changed title of data sheet from cym62177dv30 to cy62177dv30 added second chip enable (ce 2 ) added footnote #12 on page 5 *b 400960 nxr see ecn changed address of cypress se miconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? changed i sb1 from 60 and 40 ? a to 100 ? a for the l and ll versions for both the 55 and the 70 ns speed bins respectively. *c 469187 nxr see ecn converted from preliminary to final changed the i sb2(max) from 40 ? a to 50 ? a for ll version of both 45 ns and 55 ns speed bins changed the i ccdr(max) from 20 ? a to 25 ? a for ll version updated the ordering information table *d 2896036 aju 03/19/10 removed inactive parts from ordering information. updated package diagram. updated links in sales, solutions, and legal information. *e 3153110 rame 01/25/2011 updated datasheet as per template removed cy62177dv30l related info removed 70 ns speed bin related info added ordering code definitions added reference information and units of measure table *f 3329873 rame 07/27/11 removed footnote # 8 and its reference because of single package availability. updated template and styles according to current cypress standards. added acronyms and units. removed reference to an106 4 sram system guidelines. *g 3685455 memj 07/20/2012 added note 16. updated text in switching waveforms diagrams. updated package diagram.
document number : 38-05633 rev. *g revised july 20, 2012 page 13 of 13 all products and company names mentioned in this document may be the trademarks of their respective holders. cy62177dv30 mobl ? ? cypress semiconductor corporation, 2006-2012. t6he information contained herein is subject to change without notice. cypress semiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reaso nably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufact urer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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